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ARM Accredited Engineer

Last Update 19 hours ago Total Questions : 210

The ARM Accredited Engineer content is now fully updated, with all current exam questions added 19 hours ago. Deciding to include EN0-001 practice exam questions in your study plan goes far beyond basic test preparation.

You'll find that our EN0-001 exam questions frequently feature detailed scenarios and practical problem-solving exercises that directly mirror industry challenges. Engaging with these EN0-001 sample sets allows you to effectively manage your time and pace yourself, giving you the ability to finish any ARM Accredited Engineer practice test comfortably within the allotted time.

Question # 4

When programming in C, how many bytes of stack are needed to pass parameters when calling the following function?

int foo( int arg_a, int arg_b, int arg_c )

A.

0

B.

4

C.

8

D.

12

Question # 5

In the VFPv4-D32 architecture, which of the following best describes the arrangement of the registers?

A.

D0..D31 and S0..S31 are separate register banks

B.

D0..D31 overlap with S0..S63

C.

D0..D15 overlap with S0..S31, and D16..D31 do not overlap with any single-precision registers

D.

D0 overlaps with S0, D1 with S1 etc. up to D31 and S31

Question # 6

Which of the following is an advantage of the single-step debug technique?

A.

It allows a complete trace of real-time program execution to be captured

B.

It reduces the number of pins required to connect the debugger to the processor

C.

It allows examination of the system state before and after execution of a statement

D.

It requires only one change to the program source code

Question # 7

According to the AAPCS, which of the following statements is TRUE with regard to preservation of register values by a function?

A.

A function must preserve R0-R3 and R12

B.

A function must preserve R4-R11 andR13

C.

No registers may be corrupted by any function

D.

All registers may be corrupted by any function

Question # 8

Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

A.

5 cycles

B.

7 cycles

C.

8 cycles

D.

15 cycles

Question # 9

Which ARMv7 instructions are recommended to implement a semaphore?

A.

SWP, SWPB

B.

TEQ, TST

C.

STC, SBC

D.

LDREX, STREX

Question # 10

A standard performance benchmark is being run on a single core ARM v7-A processor. The performance results reported are significantly lower than expected. Which of the following options is a possible explanation?

A.

L1 Caches and branch prediction are disabled

B.

The Embedded Trace Macrocell (ETM) is disabled

C.

The Memory Management Unit (MMU) is enabled

D.

The Snoop Control Unit (SCU) is disabled

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