Coherency management between all L1 data caches

Broadcast of some inner-shared cache and TLB maintenance operations

Broadcast of some outer-shared cache and TLB maintenance operations

Coherency management between all L1 instruction caches

Coherency management between all external caches

Cortex-A8

Cortex-M3

Cortex-R4F

Cortex-A9 MPCore

VA == PA; No address translations; instructions and data are not cached

VA! = PA; No address translations; instructions may be cached but not data

VA == PA; Address translations take place; data may be cached but not instructions

VA == PA; No address translations; instructions may be cached but not data

If a TLB miss occurs

On every process switch

If the TLB reports a fault

When a page table entry is changed

Current Program Status Register (CPSR)

Contents of the Level 2 data cache

The Floating Point Status and Control Register (FPSCR)

All User mode general-purpose registers

The CP15 Multiprocessor Affinity Register

Contents of the Level 1 data cache

NEON (Advanced SIMD)

Thumb-2 technology

TrustZone (Security Extensions)

Generic Interrupt Controller

200

201

204

208

A function must preserve R0-R3 and R12

A function must preserve R4-R11 andR13

No registers may be corrupted by any function

All registers may be corrupted by any function

Cycle-accurate simulation of the CPU.

Instruction-accurate simulation of the CPU.

Simulation of user-defined memory-mapped peripherals.

Cycle-accurate simulation of the cache and memory system.

Functions that are not compliant with the ISO C library standard

Functions that are not compliant with the 1985 IEEE 754 standard for binary floating-point arithmetic

Target-dependent functions which use semihosting

Functions called implicitly by the compiler