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ARM Accredited Engineer

Last Update 12 hours ago Total Questions : 210

The ARM Accredited Engineer content is now fully updated, with all current exam questions added 12 hours ago. Deciding to include EN0-001 practice exam questions in your study plan goes far beyond basic test preparation.

You'll find that our EN0-001 exam questions frequently feature detailed scenarios and practical problem-solving exercises that directly mirror industry challenges. Engaging with these EN0-001 sample sets allows you to effectively manage your time and pace yourself, giving you the ability to finish any ARM Accredited Engineer practice test comfortably within the allotted time.

Question # 11

Which of the following is preserved in dormant mode?

A.

Core register contents

B.

CP15 (system) register settings

C.

Debug state

D.

Cache contents

Question # 12

Assume a Big-Endian (BE) memory system with the following memory contents.

Byte Address Contents

0x100 0x11

0x101 0x22

0x102 0x33

0x103 0x44

If R5 = 0x100, what are the contents of R4 after performing the following operation?

LDR R4, [R5]

A.

0x11223344

B.

0x44332211

C.

0x22114433

D.

0x33441122

Question # 13

Which of the following would enable the use of a symmetric multiprocessing (SMP) operating system?

A.

A dual-core Cortex-A9 processor

B.

A Cortex-R4 processor with a Cortex-M3 system controller

C.

A Cortex-A8 processor with a graphics processing unit (GPU)

D.

A uni-core Cortex-A5 processor with a digital signal processor (DSP)

Question # 14

What view in a debugger displays the order in which functions were called?

A.

The Call Stack view

B.

The Memory view

C.

The Registers view

D.

The Variables view

Question # 15

In an ARMv7-A processor, which control register is used to enable the Memory Management Unit (MMU)?

A.

The ACTLR

B.

The SCTLR

C.

The TTBCR

D.

The CONTEXTIDR

Question # 16

In which of the following situations would you use a mutex to avoid synchronization problems?

A.

A single-threaded application needs to manage two separate UART peripherals

B.

Two independent threads running on a single processor both need to access a single UART

C.

In a dual-core system, a UART is accessed by a single thread running on one of the processors

D.

In a dual-core system, processor A needs to access UART A and processor B needs to access UART B

Question # 17

What is the value of R2 after execution of the following instruction sequence?

MOV R3, #0xBA

MOV R2/#0x10

BIC R2, R3, R2

A.

R2 = 0xBB

B.

R2 = 0xCB

C.

R2 = 0xAA

D.

R2 = 0xCC

Question # 18

What are the values of the NZCV bits in the CPSR after executing the following instructions?

LDR R0, = 0xFFFFFFFF

ADDS R0, R0, #1

A.

0101

B.

0110

C.

1001

D.

1010

Question # 19

The disassembly of a program written in C shows calls to the function__aeabi_fadd. Which one of these compiler floating point options could have been used?

A.

Hard floating-point linkage

B.

Soft floating-point linkage without floating-point hardware

C.

Hard floating-point linkage with optimization for space

D.

Soft floating-point linkage with floating-point hardware

Question # 20

In an ARMv7-A processor with Security Extensions, which of the following mechanisms best describes the way Secure memory is protected from access by software running in a Non-secure privileged mode?

A.

The memory system has visibility of the security status of all accesses, and will reject all Non-secure accesses to Secure memory

B.

Secure memory contents are encrypted, and cannot be decrypted by Non-secure software

C.

The level 2 cache controller blocks all accesses to Secure memory when the SCR.NS bit of the processor is set

D.

The MMU generates an abort on accesses to Secure memory performed by Non-secure software

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