In the architectural evolution from FlashArray//XR2 and //XR3 to the FlashArray//XR4, Pure Storage made significant changes to the controller's rear panel and I/O design to accommodate higher performance and PCIe Gen 4 capabilities. One of the most critical changes for an Implementation Engineer to plan for during a hardware Non-Disruptive Upgrade (NDU) is the removal of the onboard, default iSCSI ports that were present on previous generations.

On //XR2 and //XR3 controllers, there were onboard Ethernet ports often used for iSCSI host connectivity without requiring a discrete PCIe adapter. However, the //XR4 controller design removes these dedicated onboard iSCSI ports to streamline the motherboard design and shift host I/O strictly to PCIe add-in cards. The //XR4 retains onboard ports specifically for Management (Mgmt) and Replication connectivity, ensuring that administrative access and array-to-array replication can still be maintained without additional hardware.

Consequently, if a customer was relying solely on the onboard ports for iSCSI traffic on their legacy //XR2 or //XR3, the Bill of Materials (BOM) for the upgrade to //XR4 must include discrete Ethernet/iSCSI PCIe cards to migrate those connections. Failure to identify this architectural difference during the pre-upgrade inventory can result in a loss of host connectivity or an inability to cable the new controllers correctly, as the expected physical ports simply will not exist on the new chassis.

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FlashArray//X R4 (and the associated //C R4) models, introduced with the PCIe Gen 4 architecture, feature support for 64Gb Fibre Channel (FC) connectivity. The default Fibre Channel Host Bus Adapters (HBAs) and the accompanying SFPs shipped with this generation are 64Gb capable, marking a significant performance leap from the 32Gb standard of the R3 generation.

While the HBAs are backward compatible with 32Gb and 16Gb SAN infrastructures, the R4 platform is explicitly marketed and technically defined by its ability to drive 64Gb line speeds to match the increased throughput of the backend PCIe Gen 4 bus and DirectFlash Modules. For an Implementation Engineer verifying the bill of materials or configuring the switch ports, it is critical to know that the R4 optics are native 64Gb. If the customer's switch infrastructure is only 16Gb or 32Gb, the ports will auto-negotiate down, but the shipped default hardware is the 64Gb standard (Option C). Option A (16Gb) and Option B (32Gb) refer to the default standards for the older //M and //X R2/R3 generations respectively.

Data evacuation is a background process used to move data off specific physical media (like a shelf or data pack) so it can be removed safely. Purity is designed to handle dynamic changes to evacuation requests efficiently.

If an evacuation is already running and additional hardware needs to be evacuated, the Implementation Engineer does not need to stop the current job or wait for it to finish. The correct procedure is to issue a new evacuation command specifying the additional packs or shelves. Purity will intelligently update the existing background job to include the new targets, queuing the data movement logic to ensure all specified hardware is cleared. This "add-to-flight" capability saves time and administrative overhead compared to cancelling and restarting the entire workflow.

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The FlashArray//XL utilizes a massive 5U chassis with a highly specific PCIe slot population architecture optimized for NVMe-oF (RDMA over Converged Ethernet - RoCE) backend connectivity. According to the FlashArray//XL Port Usage and Definitions hardware matrix, an //XL configuration supports up to two 2-port 100GbE cards explicitly dedicated to NVMe DirectFlash Shelf (DFS) connectivity.

The standard implementation procedure mandates that the primary shelf connectivity card must be installed in PCIe Slot 0 (the default slot). However, if an Implementation Engineer arrives onsite and discovers that Slot 0 is already legitimately occupied by another critical I/O card, the officially supported secondary/alternate slot for routing the backend DFS loop is PCIe Slot 6 .

Slot 5 and Slot 8 are strictly reserved for frontend host I/O connectivity (such as 32G/64G Fibre Channel HBAs). By installing the 100GbE RoCE backend expansion card into Slot 6, the engineer ensures optimal NUMA node alignment, prevents frontend/backend traffic collisions, and passes the array's mandatory pre-flight hardware_check.py validation script, allowing the new DirectFlash Shelf to initialize seamlessly.

The correct action is to refer to the “Recommended DFS Versions for Purity Releases” Knowledge Base (KB) article and, if necessary, upgrade the Purity software on the FlashArray (which updates the DFS firmware).

Compatibility: DirectFlash Shelves (DFS) run specific firmware that must be compatible with the Purity operating system running on the array controllers. If a new shelf is shipped with very recent firmware, or an old shelf is added to a new array, there may be a mismatch.

Best Practice: The "Recommended DFS Versions" KB is the definitive source of truth. The engineer must verify if the shipped Purity version supports the specific hardware revision of the shelf.

Procedure: If an upgrade is required, the engineer updates Purity on the array. Since the DFS firmware is bundled within the Purity release, upgrading the array (Option A) effectively stages the update for the shelf. Once the shelf is attached (or if attached during the upgrade), Purity automatically applies the correct firmware to the DFS modules. Skipping this check (Option B) or blindly upgrading without cross-referencing the KB (Option C) risks connectivity issues or unrecognized capacity.

The FlashArray//XL platform features a split-chassis design with a unique PCIe bus layout compared to the standard //X series. To maintain optimal performance and redundancy, the backend connectivity for DirectFlash Shelves (DFS) must be balanced across the specific PCIe root complexes managed by the dual CPUs.

For a configuration involving multiple shelves (specifically targeting the logical shelf identifiers SH8 and SH9, which often correspond to the first pair of backend loops in an //XL deployment), the validated configuration is to use PCIe Slot 0 and PCIe Slot 6 . These slots are architecturally designated for the backend NVMe-oF (RoCE) fabric cards.

Using Slot 0 (typically located on the far left) and Slot 6 (located on the right side of the chassis) ensures that the I/O load is distributed across the internal midplane and CPUs correctly. Placing cards in incorrect slots (like Slot 1 or 7, which might be reserved for host I/O or inter-controller links) can result in shelf detection failures or performance bottlenecks where one CPU is overloaded with backend traffic while the other is idle.

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During a controller upgrade (e.g., //X to //XL), the puresetup script attempts to migrate network configurations from the old controller's ports to the new controller's ports. If the script detects that certain ports configured on the source array are physically missing or "link down" on the target array, it halts to prevent a configuration mismatch that could cause a service outage.

The error message explicitly lists the affected ports. The correct resolution path is to:

Identify the services: Determine if the missing ports are critical (e.g., a replication link that hasn't been cabled yet) or non-critical (e.g., an unused interface).

Re-run with override: Execute the puresetup command again, this time appending the specific flags or arguments (often suggested in the error output or upgrade guide) to explicitly acknowledge and include those affected ports. This tells the script, "I know these ports are down/missing; proceed with the migration anyway."

This allows the upgrade logic to complete the configuration transfer so the new controller can boot, after which the engineer can physically troubleshoot the link status.

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During the preparatory phases of a FlashArray Hardware Non-Disruptive Upgrade (HWNDU), validating physical connectivity is a strict prerequisite. If an Implementation Engineer discovers that a DirectFlash Shelf (like SH9) is incorrectly cabled to CT0, the safest and most efficient remediation is to correct the cabling precisely during the physical replacement of that specific controller.

Option A (proceeding and fixing it after) is perilous because leaving the improper cabling in place could compromise backend redundancy when the partner controller assumes the full I/O load, potentially leading to a multi-pathing failure or data unavailability event during the NDU. Option B (rescheduling the entire upgrade) is an unnecessary overreaction that wastes time and resources, as the upgrade procedure itself provides the perfect window for correction.

When the Implementation Engineer initiates the failover and successfully takes CT0 offline to swap the hardware, all active I/O is safely routed through CT1. Because CT0 is completely powered down and physically isolated from the data path at this stage, the engineer can safely disconnect the miswired SAS or NVMe-oF cables and re-cable them correctly into the new CT0 hardware according to the official Pure Storage cabling matrix. This method ensures maximum redundancy is restored the moment the new controller boots, seamlessly resolving the issue without introducing any additional maintenance windows or risks.

During the initialization phase of a new Pure Storage FlashArray, the Implementation Engineer executes the puresetup newarray (or puresetup array) command via a local serial console connection. This interactive script prompts the engineer for foundational network parameters, including the management IP addresses (vir0, eth0, eth1), subnet mask, default gateway, DNS servers, and NTP servers.

By default, the puresetup utility contains built-in safety mechanisms. As soon as the IP parameters are entered, the script actively attempts to ping the provided default gateway, resolve external hostnames via the provided DNS servers, and synchronize time with the NTP targets. If the customer's top-of-rack (ToR) switches are not yet configured, the cables are unpatched, or the array is being pre-staged in a lab completely isolated from the production network, these validation tests will inevitably fail, causing the setup script to hang or reject the configuration.

To intentionally bypass this validation and force the array to accept the network parameters without testing them, the Implementation Engineer must append the --skip-network-tests flag to the setup command. Executing puresetup newarray --skip-network-tests allows the system to save the configuration to the internal database and logically initialize the cluster. The array will bring the management interfaces online locally, allowing the engineer to connect via the GUI or SSH as soon as the physical network is eventually plugged in and routed.

On the FlashArray//XL , the 4-port Fibre Channel (FC) cards are specifically supported in Slot 8 (and typically Slot 4 depending on configuration depth). The FlashArray//XL chassis (5U) utilizes a significantly different PCIe bus layout compared to the standard 3U FlashArray//X series. While the //X series typically uses Slot 0 or Slot 2 for host connectivity, the //XL architecture reserves the lower-numbered slots (0-3) primarily for backend connectivity (SAS/NVMe-oF) or specific NVRAM modules in certain configurations.

To support the high bandwidth requirements of the 4-port 32Gb FC cards, the //XL chassis provides specific x16 electrical slots. Slot 8 is a designated high-performance slot located in the upper riser section of the controller, making it the correct placement for these dense host I/O cards. Using an incorrect slot such as Slot 2 (often x8 or reserved for other functions in XL) would likely result in the card not being recognized or operating at reduced performance. Therefore, Implementation Engineers must verify the specific "slot map" for the //XL model in the FlashArray//XL Hardware Guide before seating cards, with Slot 8 being the standard supported location for the 4-port FC option among the choices provided.